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information in this document is provided in connection with intel products. intel assumes no liability whatsoever, including in fringement of any patent or copyright, for sale and use of intel products except as provided in intel?s terms and conditions of sale for such products. intel retains the right to make changes to these specifications at any time, without notice. microcontroller products may have minor varia- tions to this specification known as errata. copyright ? intel corporation, 2004 july 2004 order number: 272783-004 8xc251sa/sb/sp/sq high-performance chmos microcontroller commercial/express j real time and programmed wait state bus operation j binary-code compatible with mcs 51 j pin compatible with 44-lead plcc and 40-lead pdip mcs 51 sockets j register-based mcs 251 architecture ? 40-byte register file ? registers accessible as bytes, words, and double words j enriched mcs 51 instruction set ? 16-bit and 32-bit arithmetic and logic instructions ? compare and conditional jump instructions ? expanded set of move instructions j linear addressing j 256-kbyte expanded external code/data memory space j rom/otprom/eprom options: 16 kbytes (sb/sq), 8 kbytes (sa/sp), or without rom/otprom/eprom j 16-bit internal code fetch j 64-kbyte extended stack space j on-chip data ram options: 1-kbyte (sa/sb) or 512-byte (sp/sq) j 8-bit, ?min? 2-clock external code fetch in page mode j user-selectable configurations: ? external wait states (0-3 wait states) ? address range & memory mapping ? page mode j 32 programmable i/o lines j seven maskable interrupt sources with four programmable priority levels j three flexible 16-bit timer/counters j hardware watchdog timer j programmable counter array ? high-speed output ? compare/capture operation ? pulse width modulator ? watchdog timer j programmable serial i/o port ? framing error detection ? automatic address recognition j high-performance chmos technology j static standby to 16-mhz operation j complete system development support ? compatible with existing tools ? new mcs 251 tools available: compiler, assembler, debugger, ice j package options (pdip, plcc, and ceramic dip) j fast mcs 251 instruction pipeline this document contains information on products with ?[m] [c] '94 '95 c? as the last line of the top marking diagram. a member of the intel family of 8-bit mcs 251 microcontrollers, the 8xc251sa/sb/sp/sq is binary- code compatible with mcs 51 microcontrollers and pin compatible with 40-lead pdip and 44-lead plcc mcs 51 microcontrollers. mcs 251 microcontrollers feature an enriched instruction set, linear addressing, and efficient c-language support. the 8xc251sa/sb/sp/sq has 512 bytes or 1 kbyte of on-chip ram and is available with 8 kbytes or 16 kbytes of on-chip rom/otprom /eprom, or without rom/otprom/eprom. a variety of features can be selected by new user-programmable configurations. ? ?
2 8xc251sa/sb/sp/sq high-performance chmos microcontroller src2 (8) code address (24) clock & reset code bus (16) data ram 512 bytes or 1024 bytes code otprom/rom 8 kbytes or 16 kbytes watchdog timer timer/ counters pca serial i/o peripherals port 2 drivers p2.7:0 port 0 drivers p0.7:0 port 3 drivers p3.7:0 port 1 drivers p1.7:0 data address (24) data bus (8) memory address (16) mcs ? 251 microcontroller core system bus and i/o ports i/o ports and peripheral signals src1 (8) ib bus (8) peripheral interface interrupt handler clock & reset bus interface instruction sequencer dst (16) alu data memory interface memory data (16) register file 8xc251sa/sb/sp/sq microcontroller a4214-01 figure 1. 8xc251sa/sb/sp/sq block diagram
3 8xc251sa/sb/sp/sq high-perfo rmance chmos microcontroller temperature range with the commercial (standard) temperature option, the device operates over the temperature range 0c to +70c. the express temperature option provides -40c to +85c device operation. proliferation options table 1 lists the proliferation options. see figure 2 for the 8xc251sa/sb/sp/sq family nomenclature. table 1. proliferation options 8xc251sa/sb/sp/sq (0 ? 16 mhz; 5 v 10%) 80c251sb16 cpu-only 80c251sq16 cpu-only 83c251sa16 rom 83c251sb16 rom 83c251sp16 rom 83c251sq16 rom 87c251sa16 otprom/eprom 87c251sb16 otprom/eprom 87c251sp16 otprom/eprom 87c251sq16 otprom/eprom process information this device is manufactured on a complimentary high-performance metal-oxide semiconductor (chmos) process. additio nal process and reliability information is available in intel?s components quality and reliability handbook (order number 210997). all thermal impedance data is approximate for static air conditions at 1 watt of power dissipation. values change depending on operating conditions and application requirements. the intel packaging handbook (order number 240800) describes intel?s thermal impedance test methodology. table 2. thermal characteristics package type 44-lead plcc 46 c/w 16 c/w 40-lead pdip 45 c/w 16 c/w 40-lead ceramic dip 30.5 c/w 10 c/w package options table 3 lists the 8xc251sa/sb/sp/sq packages. table 3. pkg. definition temperature x 44 ld. plcc 0c to +70c x 40 ld. plastic dip 0c to +70c x 40 ld. ceramic dip 0c to +70c x 44 ld. plcc -40c to +85c x 40 ld. plastic dip -40c to +85c package information note: to address the fact that many of the pack - age prefix variables have changed, all package prefix variables in this document are now indicated with an "x". ja jc
program-memory options xxxxx xx x x 8 xx x packaging options temperature and burn-in options a2815-01 process information product family device speed 4 8xc251sa/sb/sp/sq high-performance chmos microcontroller figure 2. the 8xc251sa/sb/sp/sq family table 4. description of product nomenclature parameter options description temperature and burn-in options no mark commercial operating temperature range (0c to 70c) with intel standard burn-in. x express operating temperature range (-40c to 85c) with intel standard burn-in. packaging options x 44-lead plastic leaded chip carrier (plcc) x 40-lead plastic dual in-line package (pdip) x 40-lead ceramic dual in-line package (ceramic dip) program memory options 0 without rom/otprom/eprom 3 rom 7 user programmable otprom/eprom process information c chmos product family 251 8-bit control architecture device memory options sa 1-kbyte ram/8-kbyte rom/otprom/eprom sb 1-kbyte ram/16-kbyte rom/otprom/eprom or without rom/otprom/eprom sp 512-byte ram/8-kbyte rom/otprom/eprom sq 512-byte ram/16-kbyte rom/otprom/eprom or without rom/otprom/eprom device speed 16 external clock frequency notes: 1. to address the fact that many of the package prefix variables have changed, all package prefix vari - ables in the document are now indicated with an " x ". nomenclature
table 5. 8xc251sa/sb/sp/sq memory map internal address) description notes ff:ffffh ff:4000h external memory (ff:fff8h?ff:ffffh are internally decoded for configuration byte data in all rom/otprom/eprom de vices with ea# = 1. for all devices with ea# = 0, the last 8 bytes of the external address range ff:xff8h? ff:xfffh contain configuration byte information). 1 , 3 , 10 ff:3fffh ff:0000h external memory or for internal rom/ otprom/eprom devices: 16-kbytes of internal addresses as determined by the ea# pin ( ta b l e 8 ). note: 8-kbyte internal rom/otprom/eprom array addresses end at ff:1fffh. 3 , 4 , 5 fe:ffffh fe:0000h external memory 3 fd:ffffh fd:0000h reserved 6 fc:ffffh fc:0000h reserved 6 fb:ffffh 04:0000h reserved 6 03:ffffh 03:0000h reserved 6 02:ffffh 02:0000h reserved 6 01:ffffh 01:0000h external memory 3 00:ffffh 00:e000h external memory or with emap# bit = 0 this address range for 16-kbyte devices is redirected to internal rom/otprom/eprom array region. 5 , 7 00:dfffh 00:0420h external memory 7 00:041fh 00:0080h on-chip ram (512 byte ram devices end at 00:021fh 7 00:007fh 00:0020h on-chip ram 8 00:001fh 00:0000h storage for r0?r7 of register file 2 , 9 notes: 1. 18 address lines are bonded out (a15:0, a16:0, or a17:0 selected during chip configuration). 2. the special function registers (sfrs) and the regi ster file have separate internal address spaces. 3. data in this area is accessi ble by indirect addressing only. 4. devices can reset into different internal or exte rnal starting locations depending on the state of ea# and configuration register information (see ea#. see also uconfig1:0 bit definitions). 5. the 16-kbyte rom/otprom/eprom devices allow internal locations ff:2000h?ff:3fffh to map into region 00:. in this case, if ea# = 1, a data read to 00:e000h?00:ffffh is redirected to internal rom/otprom/eprom (see bit 1 in uconfig0) . this is not available for 8-kbyte rom/otprom/eprom devices. 6. this reserved area returns unspecified values and writes no data. 7. data is accessible by di rect and indirect addressing. 8. data is accessible by dire ct, indirect, and bit addressing. 9. data is accessible by direct, indirect, and register addressing. 10. eight addresses at the top of all external memory maps are reserved for current and future device configuration byte information. 5 8xc251sa/sb/sp/sq high-perfo rmance chmos microcontroller
6 8xc251sa/sb/sp/sq high-performance chmos microcontroller 8xc251sa/sb/sp/sq 44-lead plcc package ad4 / p0.4 ad5 / p0.5 ad6 / p0.6 ad7 / p0.7 ea# / v pp v ss2 ale / prog# psen# a15 / p2.7 a14 / p2.6 a13 / p2.5 p1.4 / cex1 p1.3 / cex0 p1.2 / eci p1.1 / t2ex p1.0 / t2 v ss1 v cc ad0 / p0.0 ad1 / p0.1 ad2 / p0.2 ad3 / p0.3 a4205-02 p1.5 / cex2 p1.6 / cex3 / wait# p1.7 / cex4 / a17 / wclk rst p3.0 / rxd v cc2 p3.1 / txd p3.2 / int0# p3.3 / int1# p3.4 / t0 p3.5 / t1 39 38 37 36 35 34 33 32 31 30 29 8xc251sa 8xc251sb 8xc251sp 8xc251sq view of component as mounted on pc board 7 8 9 10 11 12 13 14 15 16 17 p3.6 / wr# p3.7 / rd# / a16 xtal2 xtal1 v ss v ss2 a8 / p2.0 a9 / p2.1 a10 / p2.2 a11 / p2.3 a12 / p2.4 18 19 20 21 22 23 24 25 26 27 28 6 5 4 3 2 1 44 43 42 41 40 figure 3. 8xc251sa/sb/sp/sq 44-lead plcc package
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 v cc ad0 / p0.0 ad1 / p0.1 ad2 / p0.2 ad3 / p0.3 ad4 / p0.4 ad5 / p0.5 ad6 / p0.6 ad7 / p0.7 ea# / v pp ale / prog# psen# a15 / p2.7 a14 / p2.6 a13 / p2.5 a12 / p2.4 a11 / p2.3 a10 / p2.2 a9 / p2.1 a8 / p2.0 p1.0 / t2 p1.1 / t2ex p1.2 / eci p1.3 / cex0 p1.4 / cex1 p1.5 / cex2 p1.6 / cex3 / wait# p1.7 / cex4 / a17 / wclk rst p3.0 / rxd p3.1 / txd p3.2 / int0# p3.3 / int1# p3.4 / t0 p3.5 / t1 p3.6 / wr# p3.7 / rd# / a16 xtal2 xtal1 v ss 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 8xc251sa 8xc251sb 8xc251sp 8xc251sq view of component as mounted on pc board a4206-03 7 8xc251sa/sb/sp/sq high-perfo rmance chmos microcontroller figure 4. 8xc251sa/sb/sp/sq 40-lead pdip and ceramic dip packages
table 6. plcc/dip lead assignments listed by functional category address & data input/output name plcc dip name plcc dip ad0/p0.0 43 39 p1.0/t2 2 1 ad1/p0.1 42 38 p1.1/t2ex 3 2 ad2/p0.2 41 37 p1.2/eci 4 3 ad3/p0.3 40 36 p1.3/cex0 5 4 ad4/p0.4 39 35 p1.4/cex1 6 5 ad5/p0.5 38 34 p1.5/cex2 7 6 ad6/p0.6 37 33 p1.6/cex3 /wait# 8 7 ad7/p0.7 36 32 p1.7/cex4/a17/ wclk 9 8 a8/p2.0 24 21 p3.0/rxd 11 10 a9/p2.1 25 22 p3.1/txd 13 11 a10/p2.2 26 23 p3.4/t0 16 14 a11/p2.3 27 24 p3.5/t1 17 15 a12/p2.4 28 25 a13/p2.5 29 26 power & ground a14/p2.6 30 27 name plcc dip a15/p2.7 31 28 v cc 44 40 p3.7/rd#/a16 19 17 v cc 2 12 p1.7/cex4/a17/ wclk 9 8 v ss 22 20 v ss 1 1 v ss 2 23, 34 processor control ea#/v 35 31 name plcc dip p3.2/int0# 14 12 bus control & status p3.3/int1# 15 13 name plcc dip ea#/v pp 35 31 p3.6/wr# 18 16 rst 10 9 p3.7/rd#/a16 19 17 xtal1 21 18 ale/prog# 33 30 xtal2 20 19 psen# 32 29 8 8xc251sa/sb/sp/sq high-performance chmos microcontroller pp
table 7. lead assignments arranged by lead number plcc dip name plcc dip name 1 v ss 1 23 v ss 2 2 1 p1.0/t2 24 21 a8/p2.0 3 2 p1.1/t2ex 25 22 a9/p2.1 4 3 p1.2/eci 26 23 a10/p2.2 5 4 p1.3/cex0 27 24 a11/p2.3 6 5 p1.4/cex1 28 25 a12/p2.4 7 6 p1.5/cex2 29 26 a13/p2.5 8 7 p1.6/cex3/ wait# 30 27 a14/p2.6 9 8 p1.7/cex4/a17/ wclk 31 28 a15/p2.7 10 9 rst 32 29 psen# 11 10 p3.0/rxd 33 30 ale/prog# 12 v cc 2 34 v ss 2 13 11 p3.1/txd 35 31 ea#/v pp 14 12 p3.2/int0# 36 32 ad7/p0.7 15 13 p3.3/int1# 37 33 ad6/p0.6 16 14 p3.4/t0 38 34 ad5/p0.5 17 15 p3.5/t1 39 35 ad4/p0.4 18 16 p3.6/wr# 40 36 ad3/p0.3 19 17 p3.7/rd#/a16 41 37 ad2/p0.2 20 18 xtal2 42 38 ad1/p0.1 21 19 xtal1 43 39 ad0/p0.0 22 20 v ss 44 40 v cc 9 8xc251sa/sb/sp/sq high-perfo rmance chmos microcontroller
10 8xc251sa/sb/sp/sq high-performance chmos microcontroller signal descriptions table 8. signal descriptions signal name type description alternate function a17 o 18th address bit (a17). output to memory as 18th external address bit (a17) in extended bus applicati ons, depending on the values of bits rd0 and rd1 in configuration byte uconfig0 (see table 9 ). see also rd# and psen#. p1.7/cex4/ wclk a16 o address line 16 . see rd#. rd# a15:8 ? o address lines . upper address lines for the external bus. p2.7:0 ad7:0 ? i/o address/data lines . multiplexed lower address lines and data lines for external memory. p0.7:0 ale o address latch enable . ale signals the start of an external bus cycle and indicates that valid address info rmation is available on lines a15:8 and ad7:0. an external latch can us e ale to demultiplex the address from the address/data bus. prog# cex4:0 i/o programmable counter array (pca) input/output pins . these are input signals for the pca capture mode and output signals for the pca compare mode and pca pwm mode. p1.6:3 p1.7/a17/ wait# ea# i external access . directs program memory accesses to on-chip or off- chip code memory. for ea# = 0, all program memory accesses are off- chip. for ea# = 1, an access is to on-chip rom/otprom/eprom if the address is within the range of the on-chip rom/otprom/eprom; otherwise the access is off-chip. the value of ea# is latched at reset. for devices without on-chip rom/otprom/eprom, ea# must be strapped to ground. v pp eci i pca external clock input . external clock input to the 16-bit pca timer. p1.2 int1:0# i external interrupts 0 and 1 . these inputs set bits ie1:0 in the tcon register. if bits it1:0 in the tcon register are set, bits ie1:0 are set by a falling edge on int1#/int0#. if bits int1:0 are clear, bits ie1:0 are set by a low level on int1:0#. p3.3:2 prog# i programming pulse . the programming pulse is applied to this pin for programming the on-chip otprom. ale p0.7:0 i/o port 0 . this is an 8-bit, open-drain, bidirectional i/o port. ad7:0 p1.0 p1.1 p1.2 p1.7:3 i/o port 1 . this is an 8-bit, bidirectional i/o port with internal pullups. t2 t2ex eci cex3:0 cex4/a17/ / wait# / wclk p2.7:0 i/o port 2 . this is an 8-bit, bidirectional i/o port with internal pullups. a15:8 ? the descriptions of a15:8/p2.7:0 and ad7:0/p0.7:0 are for the nonpage-mode chip configuration (com - patible with 44-lead plcc and 40-lead dip mcs 51 microcontrollers). if the chip is configured for page- mode operation, port 0 carries the lower address bits (a7:0), and port 2 carries the upper address bits (a15:8) and the data (d7:0).
11 8xc251sa/sb/sp/sq high-perfo rmance chmos microcontroller p3.0 p3.1 p3.3:2 p3.5:4 p3.6 p3.7 i/o port 3 . this is an 8-bit, bidirectional i/o port with internal pullups. rxd txd int1:0# t1:0 wr# rd#/a16 psen# o program store enable . read signal output. this output is asserted for a memory address range that depends on bits rd0 and rd1 in configuration byte uconfig0 (see rd# and table 9 ): ? rd# o read or 17th address bit (a16). read signal output to external data memory or 17th external address bi t (a16), depending on the values of bits rd0 and rd1 in configuration byte uconfig0. (see psen# and ): p3.7/a16 rst i reset . reset input to the chip. holding this pin high for 64 oscillator periods while the oscillator is running resets the device. the port pins are driven to their reset conditions when a voltage greater than v ih1 is applied, whether or not the oscillato r is running. this pin has an inter - nal pulldown resistor, which allows the device to be reset by connect - ing a capacitor between this pin and v cc . asserting rst when the chip is in idle mode or powerdown mode returns the chip to normal operation. ? rxd i/o receive serial data . rxd sends and receives data in serial i/o mode 0 and receives data in serial i/o modes 1, 2, and 3. p3.0 t1:0 i timer 1:0 external clock inputs . when timer 1:0 operates as a counter, a falling edge on the t1:0 pin increments the count. p3.5:4 t2 i/o timer 2 clock input/output . for the timer 2 capture mode, this signal is the external clock input. for the clock-out mode, it is the timer 2 clock output. p1.0 t2ex i timer 2 external input . in timer 2 capture mode, a falling edge ini - tiates a capture of the timer 2 regi sters. in auto-reload mode, a falling edge causes the timer 2 registers to be reloaded. in the up-down counter mode, this signal determines count direction: 1=up, 0=down. p1.1 txd o transmit serial data . txd outputs the shift clock in serial i/o mode 0 and transmits serial data in serial i/o modes 1, 2, and 3. p3.1 v cc pwr supply voltage . connect this pin to the +5v supply voltage. ? v cc 2 pwr secondary supply voltage 2. this supply voltage connection is pro - vided to reduce power supply noise. connection of this pin to the +5v supply voltage is recommended. however, when using the 8xc251sb as a pin-for-pin replacement for the 8xc51fx, v ss 2 can be uncon - nected without loss of compatibility. (not available on dip) ? v pp i programming supply voltage . the programming supply voltage is applied to this pin for programming the on-chip otprom/eprom. ea# v ss gnd circuit ground . connect this pin to ground. ? table 8. signal descriptions (continued) signal name type description alternate function ? the descriptions of a15:8/p2.7:0 and ad7:0/p0.7:0 are for the nonpage-mode chip configuration (com- patible with 44-lead plcc and 40-lead dip mcs 51 microc ontrollers). if the chip is configured for page- mode operation, port 0 carries the lower address bits (a7:0), and port 2 carries the upper address bits (a15:8) and the data (d7:0).
12 8xc251sa/sb/sp/sq high-performance chmos microcontroller v ss 1 gnd secondary ground . this ground is provided to reduce ground bounce and improve power supply bypassing. connection of this pin to ground is recommended. however, when using the 8xc251sa/sb/sp/sq as a pin-for-pin replacement for the 8xc51bh, v ss 1 can be unconnected without loss of compatibility. (not available on dip) ? v ss 2 gnd secondary ground 2 . this ground is provided to reduce ground bounce and improve power supply bypass ing. connection of this pin to ground is recommended. however, when using the 8xc251sb as a pin-for-pin replacement for the 8xc51fx, v ss 2 can be unconnected without loss of compatibility. (not available on dip) ? wait# i real time wait state input. the real time wait# input is enabled by writing a logical ?1? to the wcon.0 (rtwe) bit at s:a7h. during bus cycles, the external memory system can signal ?system ready? to the microcontroller in real time by cont rolling the wait# input signal on the port 1.6 input. p1.6/cex3 wclk o wait clock output. the real time wclk output is driven at port 1.7 (wclk) by writing a logical ?1? to the wcon.1 (rtwce) bit at s:a7h. when enabled, the wclk output produces a square wave signal with a period of one-half the ocillator frequency . p1.7/cex4/ a17 wr# o write . write signal output to external memory. p3.6 xtal1 i input to the on-chip, inverting, oscillator amplifier . to use the internal oscillator, a crystal/resonator circuit is connected to this pin. if an external oscillator is used, its out put is connected to this pin. xtal1 is the clock source for internal timing. ? xtal2 o output of the on-chip, inverting, oscillator amplifier . to use the internal oscillator, a crystal/resonator circuit is connected to this pin. if an external oscillator is used, leave xtal2 unconnected. ? table 9. memory signal selections (rd1:0) rd1:0 p1.7/cex/ a17 rd# psen# wr# features 0 0 a17 rd# = a16 asserted for all addresses asserted for writes to all memory locations 256-kbyte external memory 0 1 p1.7/cex4 rd# = a16 asserted for all addresses asserted for writes to all memory locations 128-kbyte external memory 1 0 p1.7/cex4 p3.7 only asserted for all addresses asserted for writes to all memory locations one additional port pin 1 1 p1.7/cex4 asserted for 7f:ffffh asserted for 80:0000h asserted for all compati - ble mcs 51 memory locations compatible with mcs 51 microcon - trollers table 8. signal descriptions (continued) signal name type description alternate function ? the descriptions of a15:8/p2.7:0 and ad7:0/p0.7:0 are for the nonpage-mode chip configuration (com- patible with 44-lead plcc and 40-lead dip mcs 51 micr ocontrollers). if the chip is configured for page- mode operation, port 0 carries the lower address bits (a7:0), and port 2 carries the upper address bits (a15:8) and the data (d7:0).
13 8xc251sa/sb/sp/sq high-perfo rmance chmos microcontroller electrical characteristics absolute maximum ratings ambient temperature under bias: commercial ..........................................0c to +70c express .............................................-40c to +85c storage temperature ..............................-65c to +150c voltage on ea#/v pin to v ss 0 v to +13.0 v voltage on any other pin to v ss -0.5 v to +6.5 v i ol per i/o pin ..........................................................15 ma power dissipation ................................................... 1.5 w note: maximum power dissipation is based on package heat-transfer limitations, not device power consumption. operating conditions t a (ambient temperature under bias): commercial ..........................................0c to +70c express .............................................-40c to +85c v cc (digital supply voltage) ...................... 4.5 v to 5.5 v v ss .............................................................................. 0 v notice: this document contains informa - tion on products in the design phase of development. do not finalize a design with this information. revised information will be published when the product is available. verify with your local intel sales office that you have the latest datasheet before finaliz - ing a design. warning: stressing the device beyond the ?absolute maximum ratings? may cause permanent damage. these are stress ratings only. operation beyond the ?operating conditions? is not recommended and extended exposure beyond the ?operating conditions? may affect device reliability. ? pp .................. .............. ? ?
14 8xc251sa/sb/sp/sq high-performance chmos microcontroller d.c. characteristics parameter values apply to all dev ices unless otherwise indicated. table 10. dc characteristics at v cc = 4.5 ? 5.5 v symbol parameter min typical max units test conditions v il input low voltage (except ea#) -0.5 0.2v cc ? 0.1 v v il 1 input low voltage (ea#) 0 0.2v cc ? 0.3 v v ih input high voltage (except xtal1, rst) 0.2v cc + 0.9 v cc + 0.5 v v ih 1 input high voltage (xtal1, rst) 0.7v cc v cc + 0.5 v v ol output low voltage (port 1, 2, 3) 0.3 0.45 1.0 v i ol = 100 a i ol = 1.6 ma i ol = 3.5 ma ( note 1 , note 2 ) v ol 1 output low voltage (port 0, ale, psen#) 0.3 0.45 1.0 v i ol = 200 a i ol = 3.2 ma i ol = 7.0 ma ( note 1 , note 2 ) v oh output high voltage (port 1, 2, 3, ale, psen#) v cc ? 0.3 v cc ? 0.7 v cc ? 1.5 v i oh = -10 a i oh = -30 a i oh = -60 a ( note 3 ) notes: 1. under steady-state (non- transient) conditions, i ol must be externally limited as follows: maximum i ol per port pin: 10 ma maximum i ol per 8-bit port: port 0 26 ma ports 1?3 15 ma maximum total i ol for all output pins 71 ma if i ol exceeds the test conditions, v ol may exceed the related specification. pins are not guaranteed to sink current greater than the listed test conditions. 2. capacitive loading on ports 0 and 2 may cause s purious noise pulses above 0.4 v on the low-level outputs of ale and ports 1, 2, and 3. the noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins change from high to low. in applications where capacitive load - ing exceeds 100 pf, the noise pulses on these signals may exceed 0.8 v. it may be desirable to qual - ify ale or other signals with a schmitt trigger or cmos-level input logic. 3. capacitive loading on ports 0 and 2 causes the v oh on ale and psen# to drop below the specifica - tion when the address lines are stabilizing. 4. typical values are obtained using v cc = 5.0, t a = 25c and are not guaranteed.
15 8xc251sa/sb/sp/sq high-perfo rmance chmos microcontroller v oh 1 output high voltage (port 0 in external address) v cc ? 0.3 v cc ? 0.7 v cc ? 1.5 v i oh = -200 a i oh = -3.2 ma i oh = -7.0 ma v oh2 output high voltage (port 2 in external address during page mode) v cc ? 0.3 v cc ? 0.7 v cc ? 1.5 v i oh = -200 a i oh = -3.2 ma i oh = -7.0 ma i il logical 0 input cur - rent (port 1, 2, 3) -50 a vin = 0.45 v i li input leakage cur - rent (port 0) +/-10 a 0.45 < vin < v cc i tl logical 1-to-0 transi - tion current (port 1, 2, 3) -650 a vin = 2.0 v r rst rst pulldown resis - tor 40 225 k : c io pin capacitance 10 ( note 4 ) pf f osc = 16 mhz t a = 25 c i pd powerdown current 10 ( note 4 ) < 20 a i dl idle mode current 5 ( note 4 ) 7 ma f osc = 16 mhz i cc operating current 20 ( note 4 ) 45 ma f osc = 16 mhz table 10. dc characteristics at v cc = 4.5 ? 5.5 v (continued) symbol parameter min typical max units test conditions notes: 1. under steady-state (non-transient) conditions, i ol must be externally limited as follows: maximum i ol per port pin: 10 ma maximum i ol per 8-bit port: port 0 26 ma ports 1?3 15 ma maximum total i ol for all output pins 71 ma if i ol exceeds the test conditions, v ol may exceed the related specification. pins are not guaranteed to sink current greater than the listed test conditions. 2. capacitive loading on ports 0 and 2 may cause spur ious noise pulses above 0.4 v on the low-level outputs of ale and ports 1, 2, and 3. the noise is du e to external bus capacitance discharging into the port 0 and port 2 pins when these pins change from high to low. in applications where capacitive load- ing exceeds 100 pf, the noise pulses on these si gnals may exceed 0.8 v. it may be desirable to qual- ify ale or other signals with a schmi tt trigger or cmos-level input logic. 3. capacitive loading on ports 0 and 2 causes the v oh on ale and psen# to drop below the specifica- tion when the address lines are stabilizing. 4. typical values are obtained using v cc = 5.0, t a = 25c and are not guaranteed.
a4208-01 v cc v cc v cc i pd p0 ea# xtal1 v ss xtal2 rst 8xc251sa 8xc251sb 8xc251sp 8xc251sq (nc) all other 8xc251sa/sb/sp/sq pins are unconnected. 16 8xc251sa/sb/sp/sq high-performance chmos microcontroller figure 5. i pd test condition, powerdown mode, v cc = 2.0 ? 5.5v
17 8xc251sa/sb/sp/sq high-perfo rmance chmos microcontroller a.c. characteristics ta b l e 11 lists ac timing parameters for the 8xc251sa/sb/sp/sq with no wait states. external wait states can be added by extending psen#/rd#/wr# and/or by extending ale. in the table, notes 3 and 5 mark parameters affected by an ale wait state, and notes 4 and 5 mark parameters affected by a psen#/rd#/wr# wait state. figures 6 ? 11 show the bus cycles with the timing parameters. table 11. ac characteristics (capacitive loading = 50 pf) symbol parameter @ max f osc (1) f osc variable units min max min max f osc xtal1 frequency n/a n/a 0 16 mhz t osc 1/f osc @ 12 mhz @ 16 mhz n/a n/a 83.3 62.5 ns t lhll ale pulse width @ 12 mhz @ 16 mhz 73.3 52.5 (1+2m) t osc ? 10 ns ( 3 ) t avll address valid to ale low @ 12 mhz @ 16 mhz 63.3 42.5 (1+2m) t osc ? 20 ns ( 3 ) t llax address hold after ale low @ 12 mhz @ 16 mhz 10 10 10 ns t rlrh ( 2 ) rd# or psen# pulse width @ 12 mhz @ 16 mhz 156.6 115 2(1+n) t osc ? 10 ns ( 4 ) t wlwh wr# pulse width @ 12 mhz @ 16 mhz 156.6 115 2(1+n) t osc ? 10 ns ( 4 ) t llrl ( 2 ) ale low to rd# or psen# low @ 12 mhz @ 16 mhz 63.3 42.5 t osc ? 20 ns t lhax ale high to address hold @ 12 mhz @ 16 mhz 83.3 62.5 (1+2m) t osc ns ( 3 ) notes: 1. 16 mhz. 2. specifications for psen# are identical to those for rd#. 3. in the formula, m=number of wait states (0 or 1) for ale. 4. in the formula, n=number of wait states (0,1,2, or 3) for rd#/psen#/wr# 5. ?typical? specifications are untested and not guaranteed.
18 8xc251sa/sb/sp/sq high-performance chmos microcontroller t rldv ( 2 ) rd#/psen# low to valid data/instruction in @ 12 mhz @ 16 mhz 116.6 75 2(1+n) tosc ? 50 ns (4) t rhdx ( 2 ) data/instruction hold time. occurs after rd#/psen# are exerted to v oh 0 0 ns t rlaz ( 2 ) rd#/psen# low to address float typ.=0 (5) 2 typ. = 0 (5) 2 ns t rhdz1 instruction float after rd#/psen# high @ 12 mhz @ 16 mhz 10 10 10 ns t rhdz2 data float after rd#/psen# high @ 12 mhz @ 16 mhz 176.6 135 2tosc +10 ns t rhlh1 rd#/psen# high to ale high (instruction) @ 12 mhz @ 16 mhz 10 10 10 ns t rhlh2 rd#/psen# high to ale high (data) @ 12 mhz @ 16 mhz 176.6 135 2t osc + 10 ns t whlh wr# high to ale high @ 12 mhz @ 16 mhz 176.6 135 2t osc + 10 ns t avdv1 address (p0) valid to valid data/instruction in @ 12 mhz @ 16 mhz 263.2 180 4(1+m/2) t osc ? 70 ns ( 3 ) t avdv2 address (p2) valid to valid data/instruction in @ 12 mhz @ 16 mhz 278.2 195 4(1+m/2) t osc ? 55 ns ( 3 ) t avdv 3 address (p0) valid to valid instruction in @ 12 mhz @ 16 mhz 116.6 75 2t osc ? 50 ns table 11. ac characteristics (capacitive loading = 50 pf) (continued) symbol parameter @ max f osc (1) f osc variable units min max min max notes: 1. 16 mhz. 2. specifications for psen# are identical to those for rd#. 3. in the formula, m=number of wait states (0 or 1) for ale. 4. in the formula, n=number of wait states (0,1,2, or 3) for rd#/psen#/wr# 5. ?typical? specifications are untested and not guaranteed.
19 8xc251sa/sb/sp/sq high-perfo rmance chmos microcontroller t avrl ( 2 ) address valid to rd#/psen# low @ 12 mhz @ 16 mhz 146.6 105 2(1+m) t osc ? 20 ns ( 3 ) t avwl1 address (p0) valid to wr# low @ 12 mhz @ 16 mhz 156.6 115 2(1+m) t osc ? 10 ns ( 3 ) t avwl 2 address (p2) valid to wr# low @ 12 mhz @ 16 mhz 166.6 125 2(1+m) t osc ns ( 3 ) t whqx data hold after wr# high @ 12 mhz @ 16 mhz 63.3 42.5 t osc ? 20 ns t qvwh data valid to wr# high @ 12 mhz @ 16 mhz 143.6 102 2(1+n) t osc ? 23 ns ( 4 ) t whax wr# high to address hold @ 12 mhz @ 16 mhz 146.6 105 2t osc ? 20 ns table 11. ac characteristics (capacitive loading = 50 pf) (continued) symbol parameter @ max f osc (1) f osc variable units min max min max notes: 1. 16 mhz. 2. specifications for psen# are identical to those for rd#. 3. in the formula, m=number of wait states (0 or 1) for ale. 4. in the formula, n=number of wait states (0,1,2, or 3) for rd#/psen#/wr# 5. ?typical? specifications are untested and not guaranteed.
20 8xc251sa/sb/sp/sq high-performance chmos microcontroller system bus timings xtal1 ale t lhll ? a7:0 d7:0 rd#/psen# p0 p2/a16/a17 t rhdx t rhlh2 t rlrh ? t llrl ? t avll ? t llax t rldv ? t avrl ? t avdv1 ? t avdv2 ? t osc a4210-01 t lhax ? data in ? the value of this parameter depends on wait states. see the table of ac characteristics. a15:8/a16/a17 t rhdz2 t rlaz figure 6. external read data bus cycle in nonpage mode
xtal1 ale t lhll ? a7:0 t rhdz1 rd#/psen# p0 p2/a16/a17 t rhdx t rhlh1 t rlrh ? t llrl ? t avll ? t rldv ? t avrl ? t avdv1 ? t avdv2 ? t osc a4211-01 t lhax ? instruction in ? the value of this parameter depends on wait states. see the table of ac characteristics. a15:8/a16/a17 d7:0 t rlaz t llax 21 8xc251sa/sb/sp/sq high-perfo rmance chmos microcontroller figure 7. external instruction bus cycle in nonpage mode
wr# p0 p2/a16/a17 t lhll ? t wlwh ? t whlh a4179-01 xtal1 ale t osc t whqx t qvwh t whqx t avwl1 ? t avwl2 ? t whax a7:0 d7:0 data out a15:8/a16/a17 ? the value of this parameter depends on wait states. see the table of ac characteristics. t llax t lhax ? t avll ? 22 8xc251sa/sb/sp/sq high-performance chmos microcontroller figure 8. external write data bus cycle in nonpage mode
xtal1 ale t lhll ? t rhdz2 rd#/psen# p2 p0/a16/a17 t rhdx t rhlh2 t rlrh ? t llrl ? t avll ? t rldv ? t rlaz t avrl ? t avdv1 ? t avdv2 ? t osc a4212-01 t lhax ? data in ? the value of this parameter depends on wait states. see the table of ac characteristics. a15:8 a7:0/a16/a17 d7:0 t llax 23 8xc251sa/sb/sp/sq high-perfo rmance chmos microcontroller figure 9. external read data bus cycle in page mode
wr# p2 p0/a16/a17 t lhll ? t wlwh ? t whlh a4182-01 xtal1 ale t osc t whqx t qvwh t whqx t avwl1 ? t avwl2 ? t whax a15:8 d7:0 data out a7:0/a16/a17 ? the value of this parameter depends on wait states. see the table of ac characteristics. t avll ? t llax t lhax ? 24 8xc251sa/sb/sp/sq high-performance chmos microcontroller figure 10. external write data bus cycle in page mode
xtal1 ale t lhll ? a15:8 d7:0 t rhdz1 rd#/psen# p2 p0/a16/a17 t rhdx t llrl ? t avll ? t rldv ? t rlaz t avrl ? t avdv1 ? t avdv2 ? t osc a4213-02 t lhax ? instruction in a7:0/a16/a17 d7:0 instruction in a7:0/a16/a17 page miss ?? page hit ?? t avdv3 ? the value of this parameter depends on wait states. see the table of ac characteristics. ?? a page hit (i.e., a code fetch to the same 256-byte "page" as the previous code fetch) requires one state (2 t osc ); a page miss requires two states (4 t osc ). ??? during a sequence of page hits, psen# remains low until the end of the last page-hit cycle. t llax ??? 25 8xc251sa/sb/sp/sq high-perfo rmance chmos microcontroller figure 11. external instruction bus cycle in page mode
26 8xc251sa/sb/sp/sq high-performance chmos microcontroller ac characteristics ? serial port table 12. serial port timing ? shift register mode symbol parameter min max units xlxl serial port clock cycle time osc ns qvsh output data setup to clock rising edge 10t osc ? 133 ns xhqx output data hold after clock rising edge osc ns xhdx input data hold after clock rising edge 0 ns xhdv clock rising edge to input data valid 10t osc ? 133 ns , shift register mode valid valid valid valid valid valid valid valid rxd (in) rxd (out) txd 01 2 3 4 5 6 7 t qvxh t xlxl t xhdx t xhqx t xhdv a2592-02 set ti ? set ri ? t av ? ? ti and ri are set during s1p1 of the peripheral cycle following the shift of the eighth bit. figure 12. serial port waveform ? shift register mode t 12t t t 2t ? 117 t t
27 8xc251sa/sb/sp/sq high-perfo rmance chmos microcontroller external clock drive table 13. external clock drive symbol parameter min max units 1/t clcl oscillator frequency (f osc ) 16 mhz t chcx high time 20 ns t clcx low time 20 ns t clch rise time 10 ns t chcl fall time 10 ns 0.7 v cc a4119-01 0.45 v v cc ? 0.5 0.2 v cc ? 0.1 t chcl t clcx t clcl t clch t chcx figure 13. external clock drive waveforms ac inputs during testing are driven at v cc ? 0.5v for a logic 1 and 0.45 v for a logic 0. timing measurements are made at 0.45 v inputs outputs a4118-01 v ih min v ol max v cc ? 0.5 0.2 v cc + 0.9 0.2 v cc ? 0.1 a min of v ih for a logic 1 and v ol for a logic 0. figure 14. ac testing input, output waveforms
v load + 0.1 v v load ? 0.1 v timing reference points v load v oh ? 0.1 v v ol + 0.1 v for timing purposes, a port pin is no longer floating when a 100 mv change from load voltage occurs and begins to float when a 100 mv change from the loading v oh /v ol level occurs with i ol / i oh = 20 ma. a4117-01 28 8xc251sa/sb/sp/sq high-performance chmos microcontroller figure 15. float waveforms p0 psen# ale/prog# ea#/v pp 8xc251sa 8xc251sb 8xc251sp 8xc251sq a4209-01 4 mhz to 6 mhz xtal2 a0 - a7 a8 - a15 p3 p1 data (8 bits) v ss v cc v cc xtal1 programming signals address (16 bits) program/verify mode (8 bits) p2 rst figure 16. setup for programming and verifying nonvolatile memory
programming and verifying nonvolatile memory the 87c251sa/sb/sp/sq has several areas of nonvolatile memory that can be programmed and/or verified: on-chip code memory (16 kbytes), lock bits (3 bits), encryption array (128 bytes), and signature bytes (3 bytes). the 8xc251sa/sb/sp/sq user?s manual (order number: 272795) provides procedures for programming and verifying the nonvolatile memory. figure 16 shows the setup for programming and/or verifying the nonvolatile memory. table 14 lists the programming and verification operations and indicates which operations apply to the different versions of the 87c251sa/sb/sp/sq . it also specifies the signals on the programming input (prog#) and the ports. the rom/otprom/eprom mode (port 0) specifies the operation (program or verify) and the base address of the memory area. the addresses (ports 1 and 3) are relative to the base address. (on-chip memory for an 8-kbyte rom/otprom/eprom device is located at address range ff:0000h?ff:1fffh. on-chip memory for a 16-kbyte rom/otprom/eprom device is located at address range ff:0000h? ff:3fffh. the other areas of the rom/otprom/eprom are outside the memory address space and are accessible only during programming and verification.) information in figures 17 and 18 define the configuration bits. figure 19 shows the waveforms for the programming and verification cycles, and table 15 lists the timing specifica - tions. the signature bytes of the 83c251sa/sb/sp/sq rom versions and the 87c251sa/sb/sp/sq otp versions are factory programmed. table 16 lists the addresses and the contents of the signature bytes. factory-programmed rom and otprom versions of 8xc251sa/sb/sp/sq use configu - ration byte information supplied in a separate hexadecimal disk file. 8xc251sa/sb/sp/sq devices without internal rom/otprom/eprom arrays fetch configuration byte information from external application memo ry based on an internal address range of ff:fff9:8h. note: the v pp source in figure 16 must be well regulated and free of glitches. the voltage on the v pp pin must not exceed the specified maximum, even under transient conditions. 29 8xc251sa/sb/sp/sq high-perfo rmance chmos microcontroller
table 14. programming and verification modes mode 8xc251sa/s b/sp/sq prog# p0 p2 addresses p1 (high), p3 (low) notes x = 7 x = 3 program on-chip code memory y 5 pulses 68h data 0000h?3fffh (16k) 000h-1fffh (8k) 1 verify on-chip code memory y y high 28h data 0000h?3fffh (16k) 0000h-1fffh (8k) program configuration bytes 2 verify configuration bytes 2 program lock bits y 25 pulses 6bh xx 0001h?0003h 1 , 3 verify lock bits y y high 2bh data 0000h 4 program encrypt ion array y 25 pulses 6ch data 0000h?007fh 1 verify signature bytes y y high 29h data 0030h, 0031h, 0060h notes: 1. the prog# pulse waveform is shown in figure 19 . 2. factory-programmed rom, otprom and eprom versions of 8xc251sa/sb/sp/sq use config - uration byte information supplied in a sepa rate hexadecimal disk file. 8xc251sa/sb/sp/sq devices without internal rom/otprom/eprom arra ys fetch configuration byte information from external application memory based on an internal address range of ff:fff9:8h. 3. when programming the lock bits, the data bits on port 2 are don?t care. identify the lock bits with the address as follows: lb3 - 0003h, lb2 - 0002h, lb1 - 0001h 4. the three lock bits are verified in a single oper ation. the states of the lock bits appear simulta - neously at port 2 as follows: lb3 - p2.3, lb2 - p2.2. lb1 - p2.1. high = programmed. 30 8xc251sa/sb/sp/sq high-performance chmos microcontroller
uconfig0 address ff:fff8h 7 0 ucon wsa1# wsa0# xale# rd1 rd0 page# sr c bit number bit mnemonic function 7 ucon configuration byte location selector: clearing this bit causes the device to fetch configuration information from on-chip memory. setting this bit causes the device to locate configuration information based upon the state of ea# during reset (ea# = v = on-chip; ea# = v = off-chip). 6:5 wsa1#, wsa0# (see note) wait state select (for all pages ex cept 01h). wsa0# is identical to the wsa bit defined in the 8xc251sb a-step: wsa1#wsa0# description 1 1 no wait states (01: page controlled by config1) 1 0 insert 1 wait state for all pages except the 01: page 0 1 insert 2 wait states for all pages except the 01: page 0 0 insert 3 wait states for all pages except the 01: page 4 xale# extend ale: if this bit is set, the time of the ale pulse is t osc . clearing this bit extends the time of the ale pulse from t osc to 3t osc , which adds one external wait state. 3:2 rd1, rd0 rd# and psen# function select: rd1 rd0 rd# range p1.7/cex4/a17 psen# range 0 0 rd# = a16a17onlyall addresses 0 1 rd# = a16p1.7/cex4all addresses 1 0 p3.7 onlyp1.7/cex4all addresses 1 1 7f:ffffhp1.7/cex4 80:0000h 1 page# page mode select: clear this bit for page-mode (a15:8/d7:0 on p2, and a7:0 on p0). set this bit for nonpage-mode (a15:8 on p2, and a7:0/d7:0 on p0 (compatible with mcs 51 microcontrollers)). 0 src source mode/binary mode select: set this bit for source mode. clear this bit for binary mode (binary- code compatible with mcs 51 microcontrollers). 31 8xc251sa/sb/sp/sq high-perfo rmance chmos microcontroller figure 17. configuration byte 0 note: factory-programmed rom, otprom and eprom ve rsions of 8xc251sa/sb/sp/sq use configura - tion byte information supplied in a separate hexadecimal disk file. 8xc251sa/sb/sp/sq devices without internal rom/otprom/eprom arrays fetch configuration byte information from external application memory based on an internal address range of ff:fff9:8h. cc ss
32 8xc251sa/sb/sp/sq high-performance chmos microcontroller . uconfig1 address ff:fff9h 7 0 ? ? ? intr wsb wsb1# wsb0# emap# bit number bit mnemonic function 7:5 ? reserved; set these bits when writing to uconfig1. 4 intr interrupt mode: if this bit is set, interrupts push 4 bytes onto the stack (the 3 bytes of the pc register and the psw1 register). if this byte is clear, interrupts push 2 bytes onto the stack (the 2 lower bytes of the pc register). 3 wsb wait state b. only use this bit for a-step compatibility: clear this bit to generate one external wait state for memory region 01:. set this bit for no wait states for region 01:. 2:1 wsb1# , wsb0# wait states (01:xxxxh page only) wsb1# wsb0# description 11 no wait states 10 insert 1 wait state for the 01: page 01 insert 2 wait states for the 01: page 00 insert 3 wait states for the 01: page 0 emap# eprom map: clearing this bit maps the upper 8 kbytes of on-chip code memory (ff:2000h?ff:3fffh) to 00:e000h?00:ffffh. if this bit is set, the upper 8 kbytes of on-chip code memory are mapped only to ff:2000h? ff:3fffh. if this bit is set mapping does not occur. figure 18. configuration byte 1 note: factory-programmed rom and otprom versions of 8xc251sa/sb/sp/sq use configuration byte information supplied in a sepa rate hexadecimal disk file. 8x c251sa/sb/sp/sq devices without internal rom/otprom/eprom arrays fetch configur ation byte information fr om external application memory based on an internal address range of ff:fff9:8h.
prog# ea#/v pp p1, p3 a4128-01 address address (16 bits) p2 data out data in (8 bits) t avqv t ghdx t ghax t dvgl t avgl t ghgl t ghsl 12345 t glgh t shgl p0 mode mode (8 bits) t ehsh t elqv t ehqz 12.75v programming cycle verification cycle 5v 33 8xc251sa/sb/sp/sq high-perfo rmance chmos microcontroller figure 19. timing for programming and verification of nonvolatile memory
table 15. nonvolatile memory programming and verification characteristics at t a = 21 ? 27 c, v cc = 5 v, and v ss = 0 v symbol definition min max units vpp programming supply voltage 12.5 13.5 d.c. volts ipp programming supply current 75 ma fosc oscillator frequency 4.0 6.0 mhz t avgl address setup to prog# low 48t osc t ghax address hold after prog# 48t osc t dvgl data setup to prog# low 48t osc t ghdx data hold after prog# 48t osc t ehsh enable high to v pp 48t osc t shgl v pp setup to prog# low 10 s t ghsl v pp hold after prog# 10 s t glgh prog# width 90 110 s t avqv address to data valid 48t osc t elqv enable low to data valid 48t osc t ehqz data float after enable 0 48t osc t ghgl prog# high to prog# low 10 s note: notation for timing parameters: a = address d = data e = enable g = prog# h = high l = low q = data out s = supply (v pp ) v = valid x = no longer valid z = floating table 16. contents of the signature bytes address contents device type 30h 89h indicates intel devices 31h 40h indicates mcs251 core product 60h 7ah indicates 83c251sa device 60h 7bh indicates 83c251sb device 60h 4ah indicates 83c251sp device 60h 4bh indicates 83c251sq device 60h fah indicates 87c251sa device 60h fbh indicates 87c251sb device 60h cah indicates 87c251sp device 60h cbh indicates 87c251sq device 61h 55h indicates 8xc251sa/sb/sp/sq b-step products 34 8xc251sa/sb/sp/sq high-performance chmos microcontroller
35 8xc251sa/sb/sp/sq high-perfo rmance chmos microcontroller revision history the following changes appear in the -004 datasheet: 1. to address the fact that many of the package pref ix variables have changed, al l package prefix variables in the document are now indicated with an " x ". the (-003) revision of the 8xc251sa/sb/sp/sq datasheet contains information on products with ?[m] [c] '94 '95 c? as the last line of the topside marking. this datasheet replaces earlier product information. the following changes appear in the -003 datasheet: 1. uconfig0.7 (ucon) is now defined. 2. real time wait state operation is described in the datasheet. 3. memory map reserved lo cations are newly defined. the (-002) revision of the 8xc251sa/sb/sp/sq datasheet contains information on products with ?[m] [c] '94 '95 b? as the last line of the topside marking. th is datasheet replaces earlier product information. the following changes appear in the -002 datasheet: 1. a corrected pdip diagram appears on page 7. 2. a corrected formula to calculate t lhll is described on page 17. 3. the rd#/psen# waveform is changed in figure 11 on page 25.

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